1. Field of the Invention
The present invention relates to a gate processor arrangement for a simulation processor (SP) system. The simulation processor system is formed by a control processor, input and output processors, and an event transmission arrangement, and is used for the logic verification of very large scale integrated circuit (VLSICs) before production.
2. Description of the Related Art
In general, in the operation of a gate processor, it is necessary to carry out evaluation processes for evaluating the data of gates in the logic network to be verified, and to carry out inter-processor transmission for transmitting data between gate processors corresponding to sections of the logic network to be verified. First , in the prior art, when a plurality of input data to a gate is simultaneously changed, the evaluations of the same gate are duplicated and such duplicated evaluations reduce the efficiency of the system. Also, in such duplicated evaluations, a pseudo event may occur which will cause a problem in that additional devices and processes are required to deal with such a pseudo event.
Second, in the prior art, when a plurality of fan-outs of a border gate in a logic network section corresponding to a gate processor exist in another logic network section corresponding to another gate processor, a plurality of data transmissions must be carried out. This is true even if this plurality of destination gates are included in the same gate processor. This causes a problem in that a plurality of data transmissions will reduce the efficiency of the system.
Also, when the data transmissions between gate processors occur frequently in a particular later period during one step of the processing, the speed of the processing in the gate processor in question is reduced, causing a delay in the processing. This causes a problem in that such a delay also reduces the efficiency of the system.
Third, in the prior art, it is necessary to perform a double access, i.e., reading and writing, to a net status memory in a gate processor during one machine cycle. This limits the speed of the operation and thus reduces the efficiency of the system.